A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing

This article presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. proposed occupies only two major opcodes and most designed come at a near-zero energy cost. Both instruction accurate (IA) cycle (CA) model new architecture used evaluate six baseband processing test benches including FSK demodulation LoRa preamble detection. Simulation results show count improvements from 19 68 percent. Post synthesis simulations for target 22nm FD-SOI technology less than 1 percent 28 area overheads, respectively, relative baseline RV32IM design. Power peak consumption 380 µW Bluetooth LE 225 detection (BW = 500 kHz, SF 11).